Correct Common RTL Issues and Detect Clock Domain Crossing Problems

The Autocheck feature of the Questa Formal Verification tool from Mentor Graphics allows designers and verification engineers to quickly and easily verify that a design is free of many common functional design issues. This feature uses automatic assertion creation and formal sequential analysis to verify the design before a testbench is available and without user-written assertions. Common design checks performed by Autocheck include FSM checks, deadcode/stuck checks, arithmetic checks, register and bus checks to name a few. Also included is a series of checks for X verification and initialization effects in your design. Autocheck can also automatically generate an exclusion file for improving simulation code coverage thus reducing the amount of time wasted trying to hit unreachable states.
Multi-clock designs are subject to metastability, which causes mismatches between traditional simulation and silicon reality. Just adding synchronization structures is not sufficient for preventing CDC bugs in silicon. This webinar explains the importance of examining that appropriate synchronizers are in place for all clock domain crossings and analyzing the CDC timing protocols for correct synchronizer operation. Through a set of detailed examples, we show how CDC protocol failure in clock domain crossings will lead to functional problems and silicon failure.

Autocheck,Clock Domain Crossing,CDC,RTL,CDC PRoblems,Common RTL Issues,Questa,